1. Field of the Invention
The present invention relates a method of fabricating a MOS transistor on a semiconductor wafer, and more particularly, to an economic method of fabricating a MOS transistor on a semiconductor wafer.
2. Description of the Prior Art
Metal oxide semiconductor (MOS) transistors are in wide use in many electric devices. A MOS transistor has four terminals: the source, the drain, the gate and the substrate. The gate structure usually includes a polycrystalline silicon layer, or a polysilicon layer, and a silicide layer such as cobalt silicide (CoSi.sub.2). When a gate voltage greater than the threshold voltage of a MOS transistor is applied to the gate, a channel forms between the source and the drain due to strong inversion.
During the manufacturing process of a MOS transistor, the semiconductor wafer usually experiences several heating, or thermal, processes that are performed at high temperatures, such as 1000 to 1100.degree. C. Unfortunately, this leads to an increasing thermal budget and, as the line width shrinks down to 0.18, 0.15 micrometers or lower, influences the precision when controlling the doping concentration of the heavily doped drain (HDD) region.
Please refer to FIG. 1 to FIG. 4. FIG. 1 to FIG. 4 are cross-sectional diagrams of fabricating a MOS transistor on a semiconductor wafer 10 according to the prior art. As shown in FIG. 1, a gate 20 is first formed on the semiconductor wafer 10. The semiconductor wafer 10 comprises a plurality of shallow trenches 18. The gate 20 comprises a gate oxide layer 22 formed on the surface of a silicon substrate 12, and a doped polysilicon layer 24 formed on the gate oxide layer 22. A liner oxide layer 26 composed of silicon oxide is deposited to cover the surface of the silicon substrate 12 and the gate 20. A silicon nitride layer (not shown) is then formed on the liner oxide layer 26 and an etching back process is performed to etch the silicon nitride layer and the liner oxide layer 26 down to the surface of the silicon substrate 12. The remaining silicon nitride layer adjacent to the gate 20 forms spacers 28.
Subsequently, a first ion implantation process is performed using the gate 20 and the spacers 28 as hard masks to form a doped area (not shown). An annealing process is performed at a temperature of between 1000 to 1100.degree. C. (1832 to 2012.degree. F.) to form a source 14 and a drain 16.
As shown in FIG. 2, the spacers 28 and the liner oxide layer 26 are removed and a second ion implantation using the gate 20 as hard masks is performed to dope the silicon substrate 12 adjacent to the gate 20. An annealing process at a temperature of between 800 to 1000.degree. C. (1472 to 1832.degree. F.) is used to form a heavily doped drain (HDD) region 30.
As shown in FIG. 3, A silicon oxide layer 34 composed of silicon dioxide is deposited on the semiconductor wafer 10 and a low pressure chemical vapor deposition (LPCVD) at a temperature of between 750 to 800.degree. C. (1382 to 1472.degree. F.) is performed to deposit a silicon nitride layer (not shown) on the semiconductor wafer 10. A reactive ion etching process is used to form a spacer 36 adjacent to the gate 20 and portions of the silicon oxide layer 34 formed on the source 14 the drain 16 and the gate 20 are removed. A self-aligned silicide (salicide) process is performed to deposit a cobalt metal layer 38 on the surface of the silicon substrate 12 and the surface of the gate 20. A rapid thermal process (RTP) is then performed at a temperature of between 700 to 850.degree. C. (1292 to 1562.degree. F.) to form the salicide 32. The non-reacting portions of the cobalt metal layer 38 are removed.
The drawback in the prior art method is that the semiconductor wafer experiences several high-temperature thermal processes. For example, the annealing process is performed at a temperature of between 800 to 1000.degree. C. (1472 to 1832.degree. F.) to form the HDD region 30, the LPCVD process is used at a temperature of between 750 to 850.degree. C. (1382 to 1562.degree. F.) to deposit a silicon nitride layer and the rapid thermal process is performed at a temperature of between 700 to 850.degree. C. (1292 to 1562.degree. F.) to form the salicide. These high-temperature processes may result in undesirable diffusion of the dopants in the HDD region 30 and the expansion of the area of the HDD region 30, decreasing the channel length and thus inducing short channel effects. This becomes much worse when using B or BF.sub.2.sup.+ as a dopant because the atomic mass of the B or BF.sub.2.sup.+ is smaller than P.